The invention relates to methods for fabricating metal oxide semiconductors and, more particularly, to metal oxide semiconductors with lightly doped drain.
Thin film transistors (TFT) drive pixels in active matrix liquid crystal displays, active matrix organic light-emitting displays, image sensors and the like. Generally, TFT used in these apparatuses are formed of silicon semiconductor thin film. Such silicon semiconductor thin films are roughly classified into two types: amorphous silicon (a-Si) semiconductor and crystalline silicon semiconductor films.
The advantage of the crystalline silicon TFT is that the surface of a crystalline silicon layer has fewer defects than the amorphous silicon, thus the crystalline silicon TFT has a higher mobility. Currently crystalline silicon TFT is being substituted for amorphous silicon TFT in the fabrication of precise elements and pixel arrays. Compared to amorphous silicon TFT, more process steps are required to form crystalline silicon TFT. Hence, the process is more complicated and time-consuming.
FIGS. 1a to 1h are cross sections of the manufacturing process of a conventional complementary metal-oxide semiconductor. First, referring to FIG. 1a, a substrate 10 with a passivation layer 11 and an amorphous silicon layer 12 thereon is provided. The amorphous silicon layer 12 is crystallized to form a crystalline silicon layer 13, and the crystalline silicon layer 13 is patterned by photolithography to form silicon islands 13n and 13p, as shown in FIG. 1b. 
Referring to FIG. 1c, a first patterned mask layer 20 is formed on the substrate 10, exposing a part of the silicon island 13n. Next, the first mask layer 20 is used to form an n+ poly-silicon region 18n by n-type ion implantation of the exposed silicon island 13n. 
In FIG. 1d, after removal of the first mask layer 20, a second patterned mask layer 21 is formed on the substrate 10, exposing the n+ poly-silicon region 18n and a portion of the silicon island 13n adjacent to the n+ poly-silicon region 18n. Next, the second mask layer 21 is used to form an n− poly-silicon region 28 by n-type ion light implantation of the exposed portion of the silicon island 13n adjacent to the n+ poly-silicon region 18n. 
In FIG. 1e, after removal of the second mask layer 21, a third patterned mask layer 22 is formed on the substrate 10, exposing a part of the silicon island 13p. Next, the third mask layer 22 is used to form a p+ poly-silicon region 18p by p-type ion implantation of the exposed silicon island 13p. 
In FIG. 1f, after removing the third mask layer 22, an insulating film 15 and a conductive layer (not shown) are formed on the structure. The conductive layer is then patterned by photolithography to form gate electrodes 16n and 16p. The gate electrodes 16n and 16p are formed respectively on channel regions 19n and 19p. 
Referring to FIG. 1g, a silicon oxide layer 30 is formed on the structure and etched by photolithography, forming contact holes 30a. Then, referring to FIG. 1h, a metal layer is patterned by photolithography to form source/drain contact regions 35 in the contact holes 30a. 
Referring to FIG. 1i, a protection layer 40 is formed on the above structure and patterned by photolithography to form contact holes 40a exposing source/drain contact regions 35. Finally, a transparent conductive film is formed and patterned to provide a pixel electrode 50, filling the contact holes 40a. 
The conventional fabrication method described requires nine photolithography steps, which increases costs and lowers throughput and yield.
Thus, a crystalline silicon TFT manufacturing process requiring fewer photolithography steps has been disclosed. FIGS. 2a to 2f are schematic views showing such a crystalline silicon TFT manufacturing process. First, referring to FIG. 2a, a substrate 100 is provided. Next, a buffer layer 105, crystalline silicon islands 110n and 110p, an insulating layer 120, and a conductive layer 130 are sequentially formed on the substrate 100.
Next, referring to FIG. 2b, the conductive layer 130 is etched by photolithography, using a first mask layer 140 acting as mask, to form a gate electrode 132p of p-type TFT. Next, the crystalline silicon island 110p is subjected to a p-type ion implantation, with the first mask layer 140 and the gate electrode 132p acting as masks, to form a p+ poly-silicon region 180p. 
Next, referring to FIG. 2c, after removal of the first mask layer 140, the conductive layer 130 of the n-type TFT is etched using a second mask layer 150 acting as mask, to form a gate electrode 132n of the n-type TFT. Next, the crystalline silicon island 110n is subjected to a n-type ion implantation, with the second mask layer 150 and the gate electrode 132n acting as masks, to form a n+ poly-silicon region 180n. 
Next, referring to FIG. 2d, the second mask layer 150 on the gate electrode 132n is etched isotropically to remove a predetermined width thereof. The gate electrode 132n is then etched, with the remaining second mask layer 150a acting as mask, to form a smaller gate electrode 132n′. Next, the crystalline silicon island 110n is subjected to a n-type light ion implantation, with the gate electrode 132n′ acting as mask, to form a n− poly-silicon region 184.
Next, referring to FIG. 2e, the second mask layers 150 and 150a are removed. A first oxide layer 151 with first contact holes 160 is formed by photolithography. Next, source and drain contacts 162 are formed, filling the first contact holes 160. Referring to FIG. 2f, a second oxide layer 182 with a second contact hole 170 is formed on the structure. Finally, a pixel electrode 190 is formed, filling the second contact hole 170 by patterning a transparent electrode.
The fabrication method requires fewer photolithography steps. It is, however, critical to form the smaller second mask layer 150a by etching. That is, the narrow process window of the conventional crystalline silicon TFT increases the difficulty of manufacture.
Therefore, on the premise that the process window is unlimited and the process complexity is not increased, a metal oxide semiconductor, such as TFT, manufacturing process with fewer photolithography steps is called for.